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  max17000a complete ddr2 and ddr3 memory power-management solution 19-4307; rev 3; 4/13 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maximintegrated.com. general description the max17000a pulse-width modulation (pwm) con-troller provides a complete power solution for notebook ddr, ddr2, and ddr3 memory. it comprises a step- down controller, a source-sink ldo regulator, and a ref- erence buffer to generate the required vddq, vtt, and vttr rails. the vddq rail is supplied by a step-down converter using maxims proprietary quick-pwm? controller. the high-efficiency, constant-on-time pwm controller han- dles wide input/output voltage ratios (low duty-cycle applications) with ease and provides 100ns response to load transients while maintaining a relatively constant switching frequency. the quick-pwm architecture cir- cumvents the poor load-transient timing problems of fixed-frequency current-mode pwms while also avoid- ing the problems caused by widely varying switching frequencies in conventional constant-on-time and con- stant-off-time pwm schemes. the controller senses the current to achieve an accurate valley current-limit pro- tection. it is also built in with overvoltage, undervoltage, and thermal protections. the max17000a can be set to run in three different modes: power-efficient skip mode, low-noise forced-pwm mode, and standby mode to support memory in notebook computer stand- by operation. the switching frequency is programma- ble from 200khz to 600khz to allow small components and high efficiency. the vddq output voltage can be set to a preset 1.8v or 1.5v, or be adjusted from 1.0v to 2.5v by an external resistor-divider. this output has 1% accuracy over line-and-load operating range. the max17000a includes a 2a source-sink ldo reg- ulator for the memory termination vtt rail. this vtt reg- ulator has a 5mv deadband that either sources or sinks, ideal for the fast-changing load burst present in memory termination applications. this feature also reduces output capacitance requirements. the vttr reference buffer sources and sinks 3ma, providing the reference voltage needed by the memory controller and devices on the memory bus. the max17000a is available in a 24-pin, 4mm x 4mm, thin qfn package. applications notebook computersddr, ddr2, and ddr3 memory supplies sstl memory supplies features ? smps regulator (vddq) quick-pwm with 100ns load-step responseoutput voltages?reset 1.8v, 1.5v, or adjustable 1.0v to 2.5v 1% v out accuracy over line and load 26v maximum input voltage ratingaccurate valley current-limit protection 200khz to 600khz switching frequency ? source/sink linear regulator (vtt) ?a peak source/sinklow-output capacitance requirement output voltages-preset vddq/2 or refin adjustable from 0.5v to 1.5v ? soft-start/soft-shutdown ? smps power-good window comparator ? vtt power-good window comparator ? selectable overvoltage protection ? undervoltage/thermal protections ? ?ma reference buffer (vttr) 2324 22 21 87 9 pgood1 vttsvttr 10 ovp bstdh ton dlcsh 1 2 skip 456 *ep *exposed pad 17 18 16 14 13 v cc shdn refinvtti vtt pgnd2 max17000a pgood2 lx 3 15 agnd 20 11 fb pgnd1 19 12 csl v dd thin qfn 4mm x 4mm top view stdby pin configuration ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. part temp range pin-package max17000aetg+ -40 c to +85 c 24 thin qfn-ep* quick-pwm is a trademark of maxim integrated products, inc. downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 2 maxim integrated absolute maximum ratings electrical characteristics (v in = 12v, v cc = v dd = v shdn = v refin = 5v, v csl = 1.8v, stdby = skip = agnd, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ton to pgnd1 .......................................................-0.3v to +28v v dd to pgnd1..........................................................-0.3v to +6v v cc to v dd ............................................................-0.3v to +0.3v ovp to agnd ...........................................................-0.3v to +6v shdn , stdby , skip to agnd .................................-0.3v to +6v refin, fb, pgood1, pgood2 to agnd ................................-0.3v to (v cc + 0.3v) csh, csl to agnd ....................................-0.3v to (v cc + 0.3v) dl to pgnd1..............................................-0.3v to (v dd + 0.3v) bst to pgnd1...........................................................-1v to +34v bst to lx..................................................................-0.3v to +6v dh to lx ....................................................-0.3v to (v bst + 0.3v) bst to v dd .............................................................-0.3v to +28v vtti to pgnd2 .........................................................-0.3v to +6v vtt to pgnd2 ............................................-0.3v to (v tti + 0.3v) vtts to agnd............................................-0.3v to (v cc + 0.3v) vttr to agnd ..........................................-0.3v to (v csl + 0.3v) pgnd1, pgnd2 to agnd.....................................-0.3v to +0.3v continuous power dissipation (t a = +70c) 24-pin, 4mm x 4mm thin qfn (derated 27.8mw/c above +70c) ..........................2222mw operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units pwm controller v in 3 26 input voltage range v cc , v dd 4.5 5.5 v fb = agnd 1.485 1.500 1.515 fb = v cc 1.782 1.800 1.818 output-voltage accuracy v csl v in = 4.5v to 26v, skip = v cc fb = adj 0.99 1.000 1.01 v output-voltage range v csl 1 2.7 v load regulation error v csh - v csl = 0 to 18mv, skip = v cc 0.1 % line regulation error v dd = 4.5v to 5.5v, v in = 4.5v to 26v 0.25 % soft-start ramp time t sstart rising edge of shdn 1.4 2.1 ms soft-stop ramp time t sstop falling edge of shdn 2.8 ms soft-stop threshold 25 mv r ton = 96.75k  (600khz), 167ns nominal -15 +15 r ton = 200k  (300khz), 333ns nominal -10 +10 on-time accuracy (note 2) t on v in = 12v, v csl = 1.2v r ton = 303.25k  (200khz), 500ns nominal -15 +15 % downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 3 maxim integrated parameter symbol conditions min typ max units minimum off-time t off(min) (note 2) 250 350 ns quiescent supply current (v dd ) i dd fb forced above 1.0v, stdby = agnd or v cc, t a = +25c 0.01 1.00 a fb forced above 1.0v (pwm, vtt, and vttr blocks); stdby = v cc 2 4 ma quiescent supply current (v cc ) i cc fb forced above 1.0v (pwm and vttr blocks); stdby = agnd 900 1500 a shutdown supply current (v dd + v cc ) i cc + i dd shdn = agnd, t a = +25c 0.01 5 a ton shutdown current i ton shdn = agnd, v in = 26v, v dd = 0 or 5v, t a = +25c 0.01 1.00 a linear regulator (vtt) vtti input voltage range v tti 1.0 2.8 v vtti supply current i vtti vtti = 2.8v, refin = 1.4v, no load 10 50 a vtti shutdown current shdn = agnd, t a = +25c 10 a refin input bias current vtti = 2.8v, refin = 1.4v, t a = +25c -50 +50 na refin range v refin 0.5 1.5 v refin disable threshold v cc - 0.3 v high-side on-resistance (source, i vtt = 0.1a) 0.12 0.25 vtt internal mosfet low-side on-resistance (sink, i vtt = 0.1a) 0.18 0.36  v refin = 1v, i vtt = +50a -5 +5 vtt output-accuracy source load (v refin - 5mv) or (v csl /2 - 5mv) to vtts, vtt = vtts v refin = 0.5v to 1.5v, i vtt = +300ma -5 mv v refin = 1v, i vtt = -50a -5 +5 vtt output-accuracy sink load (v refin + 5mv) or (v csl /2 + 5mv) to vtts, vtt = vtts v refin = 0.5v to 1.5v, i vtt = -300ma +5 mv vtt load regulation -50a to -1a  i vtt  +50a to +1a 13 17 mv/a vtt line regulation 1.0v  v tti  2.8v, i vtt = 100ma 1 mv source 2 4 vtt current limit sink -4 -2 a vtt current-limit soft-start time with respect to internal vtt_en sign al 160 s vtt discharge mosfet ovp = v cc 16  vtts input current t a = +25c 0.1 1.0 a electrical characteristics (continued)(v in = 12v, v cc = v dd = v shdn = v refin = 5v, v csl = 1.8v, stdby = skip = agnd, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) (note 1) downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 4 maxim integrated electrical characteristics (continued)(v in = 12v, v cc = v dd = v shdn = v refin = 5v, v csl = 1.8v, stdby = skip = agnd, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units reference buffer (vttr) i vtt = 1ma -10 +10 vttr output accuracy (adj) refin to vttr i vtt = 3ma -20 +20 i vtt = 1ma -10 +10 vttr output accuracy (preset) v csl /2 to vttr i vtt = 3ma -20 +20 mv vttr maximum recommended current source/sink 5 ma fault detection (smps) smps ovp and pgood1 upper trip threshold 12 15 18 % smps ovp and pgood1 upper trip threshold fault-propagation delay t ovp fb forced 25mv above trip threshold 10 s smps output undervoltage fault-propagation delay t uvp 200 s smps pgood1 lower trip threshold measured at fb, hysteresis = 25mv -12 -15 -18 % pgood1 lower trip threshold propagation dela y t pgood1 fb forced 50mv below pgood1 trip threshold 10 s pgood1 output low voltage i sink = 3ma 0.4 v pgood1 leakage current i pgood1 fb = 1v (pgood1 high impedance), pgood1 forced to 5v, t a = +25c 1 a ton por threshold v por(in) rising edge, pwm disabled below this level; hysteresis = 200mv 3.0 v fault detection (vtt) pgood2 upper trip threshold hysteresis = 25mv 8 10 13 % pgood2 lower trip threshold hysteresis = 25mv -13 -10 -8 % pgood2 propagation dela y t pgood2 vtts forced 50mv beyond pgood2 trip threshold 10 s pgood2 fault latch delay vtts forced 50mv beyond pgood2 trip threshold 5 ms pgood2 output low voltage i sink = 3ma 0.4 v pgood2 leakage current i pgood2 vtts = v refin (pgood2 high impedance), pgood2 forced to 5v, t a = +25c 1 a fault detection thermal-shutdown threshold t shdn hysteresis = 15 c 160 c v cc undervoltage lockout threshold v uvlo(vcc) rising edge, ic disabled below this level hysteresis = 200mv 3.8 4.1 4.4 v csl discharge mosfet ovp = v cc 16  downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 5 maxim integrated electrical characteristics (continued)(v in = 12v, v cc = v dd = v shdn = v refin = 5v, v csl = 1.8v, stdby = skip = agnd, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units current limit valley current-limit threshold v limit v csh - v csl 17 20 25 mv current-limit threshold (negative) v neg v csh - v csl , skip = v cc -23 mv current-limit threshold (zero crossing) v zx v pgnd1 - v lx 1 mv smps gate drivers dh gate-driver on-resistance r dh bst - lx forced to 5v 1.5 5.0  dl high 1.5 5.0 dl gate-driver on-resistance r dl dl low 0.6 3.0  dh gate-driver source/ sink current i dh dh forced to 2.5v, bst - lx forced to 5v 1 a i dl(src) dl forced to 2.5v 1 dl gate-driver source/ sink current i dl(snk) dl forced to 2.5v 3 a dl rising, t a = +25c 10 25 dead time t dead dl falling, t a = +25c 15 35 ns internal bst switch on-resistance r bst i bst = 10ma, v dd = 5v internal design target 4.5  lx, bst leakage current v bst = v lx = 26v, shdn = agnd, t a = +25c 0.001 20 a inputs and outputs logic-input threshold shdn , stdb , skip , ovp, rising edge hysteresis = 300mv/600mv (min/max) 1.30 1.65 2.00 v logic-input current shdn , stdb , skip = 0 or v cc , t a = +25c -1 +1 a input leakage current csh = 0 or v cc , t a = +25c -1 +1 a input bias current csl = 0 or v cc 55 100 a downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 6 maxim integrated electrical characteristics(v in = 12v, v cc = v dd = v shdn = v refin = 5v, v csl = 1.8v, stdby = skip = agnd, t a = -40? to +85? , unless otherwise noted.) (note 1) parameter symbol conditions min max units pwm controller v in 3 26 input voltage range v cc , v dd 4.5 5.5 v fb = agnd 1.485 1.520 fb = v cc 1.782 1.820 output-voltage accuracy v csl v in = 4.5v to 26v, skip = v cc fb = adj 0.990 1.020 v r ton = 96.75k  (600khz), 167ns nominal -15 +15 r ton = 200k  (300khz), 333ns nominal -10 +10 on-time accuracy (note 2) t on v in = 12v, v csl = 1.2v r ton = 303.25k  (200khz), 500ns nominal -15 +15 % minimum off-time t off(min) (note 2) 350 ns fb forced above 1.0v (pwm, vtt, and vttr blocks); stdb = v cc 4 ma quiescent supply current (v cc ) i cc fb forced above 1.0v (pwm and vttr blocks); stdb = agnd 1500 a linear regulator (vtt) vtti input voltage range v vtti 1.0 2.8 v vtti supply current i vtti vtti = 2.8v, refin = 1.4v, no load 50 a refin range v refin 0.5 1.5 v refin disable threshold v cc - 0.3 v high-side on-resistance (source, i vtt = 0.1a) 0.25 vtt internal mosfet low-side on-resistance (sink, i vtt = 0.1a) 0.36  vtt load regulation -50a to -1a  i vtt  +50a to +1a 17 mv/a downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 7 maxim integrated electrical characteristics (continued)(v in = 12v, v cc = v dd = v shdn = v refin = 5v, v csl = 1.8v, stdby = skip = agnd, t a = -40? to +85? , unless otherwise noted.) (note 1) parameter symbol conditions min max units reference buffer (vttr) i vtt = 1ma -10 +10 vttr output accuracy (adj) refin to vttr i vtt = 3ma -20 +20 mv i vtt = 1ma -10 +10 vttr output accuracy (preset) v csl /2 to vttr i vtt = 3ma -20 +20 mv fault detection (smps) pgood1 output low voltage i sink = 3ma 0.4 v fault detection (vtt) pgood2 output low voltage i sink = 3ma 0.4 v fault detection v cc undervoltage-lockout threshold v uvlo(vcc) rising edge, ic disabled below this level; hysteresis = 200mv 4.0 4.4 v current limit valley current-limit threshold v limit v csh - v csl 15 25 mv smps gate drivers dh gate-driver on-resistance r dh bst - lx forced to 5v 5  dl high 5 dl gate-driver on-resistance r dl dl low 3  dl rising 10 dead time t dead dl falling 15 ns inputs and outputs logic-input threshold shdn , stdby , skip ovp, rising edge hysteresis = 300mv/600mv (min/max) 1.3 2 v note 1: limits are 100% production tested at t a = +25c. maximum and minimum limits over temperature are guaranteed by design and characterization. note 2: on-time and off-time specifications are measured from 50% point at the dh pin with lx = gnd, v bst = 5v, and a 250pf capacitor connected from dh to lx. actual in-circuit times might differ due to mosfet switching speeds. downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 8 maxim integrated typical operating characteristics (max17000a circuit of figure 1, v in = 12v, v dd = v cc = 5v, skip = gnd, t a = +25c, unless otherwise noted.) smps 1.5v efficiency vs. load current max17000a toc01 load current (a) efficiency (%) 1 0.1 20 30 40 50 60 70 80 90 100 10 0.01 10 v in = 7v skip mode stdby = low skip mode stdby = high pwm mode stdby = high or low smps 1.5v efficiency vs. load current max17000a toc02 load current (a) efficiency (%) 1 0.1 20 30 40 50 60 70 80 90 100 10 0.01 10 v in = 12v skip mode stdby = low skip mode stdby = high pwm mode stdby = high or low smps 1.5v efficiency vs. load current max17000a toc03 load current (a) efficiency (%) 1 0.1 20 30 40 50 60 70 80 90 100 10 0.01 10 v in = 20v skip mode stdby = low skip mode stdby = high pwm mode stdby = high or low smps 1.5v output voltage vs. load current max17000a toc04 load current (a) output voltage (v) 0.1 1 0.01 1.50 1.511.49 0.001 10 pwm mode v in = 12v skip mode smps switching frequency vs. load current max17000a toc05 load current (a) switching frequency (khz) 468 2 100 50 200150 300250 350 0 01 0 v in = 12v v out = 1.5v pwm mode skip mode smps valley-current limit vs. input voltage max17000a toc06 input voltage (v) current limit (a) 12 16 20 24 8 9.75 10.00 10.25 10.50 9.50 42 8 r sense = 2m no-load supply current vs. input voltage max17000a toc07 input voltage (v) supply current (ma) 12 16 20 24 8 0.1 1 10 100 0.01 42 8 pwm mode, i cc + i dd stdby = high, skip mode, i cc + i dd stdby = low, skip mode, i cc + i dd skip mode, i in pwm mode, i in no load preset 1.5v output voltage distribution max17000a toc08 output voltage (v) sample percentage (%) 1.500 1.505 1.495 10 20 30 40 50 0 1.490 1.510 sample size = 150 t a = +85 c t a = +25 c downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 9 maxim integrated startup waveform (heavy load) max17000a toc09 200 s/div pgood1 shdn: 5v/divvddq: 500mv/div vtt: 500mv/div vttr: 500mv/div pgood1: 2v/divi lx : 5a/div dl: 5v/div r load = 0.25 skip = gnd vttr vtt vddq dl i lx shdn shutdown waveform (discharge mode enabled) max17000a toc10 400 s/div dl pgood2: 5v/divpgood1: 5v/div shdn: 10v/div i lx : 2a/div dl: 5v/divvddq: 2v/div vtt: 1v/div vttr: 1v/div vttr vtt vddq pgood1 pgood2 i lx shdn standby transition waveform max17000a toc11 100 s/div dl ton ton: 1v/divdl: 5v/div lx: 10v/div i lx : 2a/div stdby: 5v/divvddq: 1v/div vtt: 1v/div vtt vddq i lx lx stdby i vtt = 50ma standby transition waveform max17000a toc12 10 s/div dl ton dl: 5v/divlx: 10v/div i lx : 2a/div stdby: 5v/divvddq: 1v/div vtt: 1v/div ton: 1v/div vtt vddq i lx lx stdby smps load-transient response (pwm mode) max17000a toc13 20 s/div i load : 5a/div i lx : 5a/div vddq: 50mv/divlx: 10v/div vddq i lx i load lx smps load-transient response (skip mode) max17000a toc14 20 s/div i load : 5a/div i lx : 5a/div vddq: 50mv/divlx: 10v/div vddq i lx i load lx typical operating characteristics (continued) (max17000a circuit of figure 1, v in = 12v, v dd = v cc = 5v, skip = gnd, t a = +25c, unless otherwise noted.) downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 10 maxim integrated typical operating characteristics (continued) (max17000a circuit of figure 1, v in = 12v, v dd = v cc = 5v, skip = gnd, t a = +25c, unless otherwise noted.) output overload waveform max17000a toc15 400 s/div pgood2: 2v/divpgood1: 2v/div i lx : 10a/div dl: 5v/divvddq: 1v/div vtt: 1v/div vttr: 1v/div vddq vtt vttr dl i lx pgood2pgood1 vtt voltage vs. source/sink load current max17000a toc16 load current (a) vtt voltage (v) -0.5 0 0.5 1.5 1.0 -1.5 -1.0 0.740.73 0.760.75 0.780.77 0.790.72 -2.0 2.0 v tti = 1.5v vtt offset voltage distribution at 300ma load max17000a toc17 offset voltage (mv) sample percentage (%) -10.0 -7.5 -12.5 10 20 30 40 50 0 -15.0 -5.0 sample size = 150 t a = +85 c t a = +25 c vtt overload fault waveforms (5ms timer) max17000a toc20 1ms/div vttr: 1v/divpgood1: 2v/div pgood2: 2v/div dl: 5v/divi lx : 2a/div vddq: 2v/divvtt: 1v/div vddq vtt vttr dl i lx pgood1pgood2 vtt source current limit max17000a toc18 current limit (a) sample percentage (%) 3.0 3.5 2.5 10 20 30 40 50 0 2.0 4.0 sample size = 150 t a = +85 c t a = +25 c vtt sink current limit max17000a toc19 current limit (a) sample percentage (%) -3.0 -2.5 -3.5 10 20 30 40 50 0 -4.0 -2.0 sample size = 150 t a = +85 c t a = +25 c downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 11 maxim integrated vtt load-transient response (source) i vtt between 10ma and 1.5a max17000a toc21 20 s/div i vtt : 1a/div vtt: 20mv/div vtt_ac i vtt vddq = 1.5v vtt load-transient response (sink) max17000a toc22 20 s/div i vtt : 1a/div vtt: 20mv/div vtt_ac i vtt vddq = 1.5v vtt load-transient response (source-sink) max17000a toc23 20 s/div i vtt : 1a/div vtt: 50mv/div vtt_ac i vtt vddq = 1.5v vttr output voltage vs. load current max17000a toc24 load current (ma) output voltage (v) -2 0 2 4 -4 0.73 0.750.74 0.71 0.72 0.77 0.780.76 0.790.70 -6 6 typical operating characteristics (continued) (max17000a circuit of figure 1, v in = 12v, v dd = v cc = 5v, skip = gnd, t a = +25c, unless otherwise noted.) downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 12 maxim integrated pin description pin name function 1 ovp ovp mode control. this input selectively enables/disables the smps ov protection feature and output discharge mode. when enabled, the smps ov protection feature is ena bled. connect ovp to the following voltage levels for the desired function: high (> 2.4v) = enable smps ov protection, and smps and vtt discharge fets. low (gnd) = disable smps ov protection, and smps and vtt discharge fets. 2 pgood1 open-drain power-good output. pgood1 is low when the smps output volt age is more than 15% (typ) beyond the normal regulation point, in standby, in shu tdown, and during soft-start. after the soft-start circuit has terminated, pgood1 becomes high impedance if the smps output is in regulation. 3 pgood2 open-drain power-good output. pgood2 is low when the vtt output voltag e is more than 10% (typ) beyond the normal regulation point, in standby, in shutdown, and during soft-start. after the smps soft-start circuit has terminated, pgood2 becomes hig h impedance if the vtt output is in regulation. 4 stdb standby control input. when shdn is high and stdb is low, the max17000a turns off the vtt output (high-z). when stdb is high, normal smps operation resumes and the vtt output is enabled. 5 vtts sense pin for termination supply output. normally connected to the vtt pin to allow accurate regulation to v csl /2 or the refin voltage. 6 vttr termination reference buffer output. vttr tracks v csl /2 when refin is connected to v cc . vttr tracks v refin when a voltage between 0.5v to 1.5v is set at refin. decouple vttr to ag nd with a 0.33f ceramic capacitor. 7 pgnd2 power ground for vtt. connect pgnd2 externally to the undersi de of the exposed pad. 8 vtt termination power-supply output. connect vtt to vtts to regulate the vtt vol tage to the vtts regulation setting. 9 vtti termination power-supply input. vtti is the input power supply to the vtt linear regulator. normally connected to the output of the smps regulator for ddr applications. 10 refin external reference input. refin sets the feedback regulation voltage (v ttr = vtts = v refin ) of the max17000a. connect refin to v cc to use the internal v csl /2 divider. connect a 0.5v to 1.5v voltage input to set the adjustable output for v tt, vtts, and vttr. 11 fb feedback input for smps output. connect to v cc for a fixed +1.8v output or to agnd for a fixed +1.5v output. for an adjustable output (1.0v to 2.7v), connect fb to a resistive d ivider from the output voltage. fb regulates to +1.0v. 12 csl negative input of the pwm output current-sense and supply input for vttr. connect csl to th e negative side of the output current-sensing resistor or the filte ring capacitor if the dc resistance of the output inductor is utilized for current sensing. csl is also the path for the internal 16  discharge mosfet when v cc uvlo occurs with ovp enabled. 13 csh positive input of the pwm output current sense. connect csh to the posit ive side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is utilized for current sensing. downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 13 maxim integrated pin description (continued) pin name function 14 ton switching frequency setting input. an external resistor between the input po wer source and this pin sets the switching frequency per phase according to the followin g equation: t sw = c ton x (r ton + 6.5k  ) where c ton = 16.26pf. ton is high impedance in shutdown. 15 dh high-side gate-driver output. swings from lx to bst. dh is low when in shutdown or uvlo. 16 lx inductor connection. connect lx to the switched side of the inductor as sh own in figure 1. 17 bst boost flying capacitor connection. connect to an external 0.1f, 6v cap acitor as shown in figure 1. the max17000a contains an internal boost switch. 18 dl synchronous-rectifier gate-driver output. dl swings from v dd to pgnd1. 19 v dd supply voltage input for the dl gate driver and 3.3v reference/analog supply. conne ct to the system supply voltage (+4.5v to +5.5v). bypass v dd to power ground with a 1f or greater ceramic capacitor. 20 pgnd1 power ground. ground connection for the low-side mosfet gate driver . 21 agnd analog ground. connect backside eposed pad to agnd. 22 skip pulse-skipping control input. this input determines the mode of operation under normal steady- state conditions and dynamic output-voltage transitions: high (> 2.4v) = forced-pwm operation low (agnd) = pulse-skipping mode 23 v cc controller supply voltage. connect to a 4.5v to 5.5v source. bypass v cc to agnd with a 1f or greater ceramic capacitor. 24 shdn shutdown control input. connect to v cc for normal operation. when shdn is pulled low, the max17000a slowly ramps down the output voltage to gr ound. when the internal target voltage reaches 25mv, the controller forces dl low, and enters the low current (1a) shutdown state. when discharge mode is enabled by ovp (ovp = high), the csl and vtt in ternal 16  discharge mosfets are enabled in shutdown. when discharge mode is disabled b y ovp (ovp = low), lx, vtt, and vttr are high impedance in shutdown. a rising edge on shdn clears the fault ov protection latch. ep exposed pad. connect backside eposed pad to agnd. downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 14 maxim integrated standard application circuits the max17000a standard application circuit (figure 1)generates the vddq, vtt, and vttr rails for ddr, ddr2, or ddr3 in a notebook computer. see table 1 forcomponent selections. table 2 lists the component man- ufacturers. table 3 is the operating mode truth table. v out = 1.5v to 1.8v at 10a v out = 1.5v to 1.8v at 6a component v in = 7v to 20v (300khz) v in = 7v to 16v (500khz) input capacitor (2x) 10f, 25vtaiyo yuden tmk432bj106km 10f, 25vtaiyo yuden tmk432bj106km output capacitor (2x) 330f, 2.5v ,12m (c2 case) sanyo 2r5tpe330mcc2 (2x) 220f, 2.5v, 21m (b2 case) sanyo 2r5tpe220mlb inductor 1.4h, 12a, 3.4m (typ) sumida cdep105(l)np-1r4 1.4h, 12a, 3.4m (typ) sumida cdep105(l)np-1r4 current-sensing resistor 2m , 0.5w (2010) vishay wsl20102l000fea 3m , 0.5w (2010) vishay wsl20103l000fea mosfets 30v, 20a n-channel mosfet (high side)fairchild fdms8690; 30v, 40a n-channel mosfet (low side) fairchild fdms8660s 30v 20a n-channel mosfet (high side)fairchild fdms8690; 30v 40a n-channel mosfet (low side) fairchild fdms8660s table 1. component selection for standard applications supplier phone website inductors dale (vishay) 402-563-6866 (usa) www.vishay,com nec/tokin america, inc. 510-324-4110 (usa) www.nec-tokinamerica.com panasonic corp. 65-231-3226 (singapore), 408-749-9714 (usa) www.panasonic.com sumida corp. 408-982-9660 (usa) www.sumida.com toko america, inc. 858-675-8013 (usa) www.tokoam.com capacitors avx corp. 843-448-9411 (usa) www.avxcorp.com kemet corp. 408-986-0424 (usa) www.kemet.com panasonic corp. 65-231-3226 (singapore), 408-749-9714 (usa) www.panasonic.com sanyo electric co., ltd. 81-72-870-6310 (japan), 619-661-6835 (usa) www.sanyodevice.com taiyo yuden 03-3667-3408 (japan), 408-573-4150 (usa) www.t-yuden.com tdk corp. 847-803-6100 (usa), 81-3-5201-7241 (japan) www.component.tdk.com sensing resistors vishay 402-563-6866 (usa) www.vishay,com mosfet fairchild semiconductor 800-341-0392 (usa) www.fairchildsemi.com diodes central semiconductor corp. 631-435-1110 www.centralsemi.com nihon inter electronics corp. 81-3-3343-84-3411 (japan) www.niec.co.jp table 2. component suppliers downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 15 maxim integrated shdn stdby skip operation 1 l  h l  h x smps output ramps up in skip mode with a 1.4ms (typ) ramp time. pgo od1 is held low until the smps output is in regulation. vtt and vttr ramp up to the final voltage based on v csl /2 or v refin . pgood2 i s he ld low unti l vtt is in regulation. 2 l  h l x smps output ramps up in skip mode with a 1.4ms ramp time. pgood1 i s held low until the smps output is in regulation. vtt remains off throughout since stdb is low. pgood2 stays low throughout. vttr ramps up to the final voltage based on v csl /2 or v refin . 3 h l  h x standby mode is exited and the full current capability of the ma x17000a is available. vtt ramps up after the internal smps block is ready. vtt ramps to the final vo ltage based on v csl /2 or v refin . pgood2 goes high when vtt is in regulation. 4 h h h smps is in forced-pwm mode. vtt and vttr are enabled. pgood1 is high when the smps output is in regulation. pgood2 is high when vtt is in regulation. 5 h h l smps is in skip mode. vtt and vttr are enabled. pgood1 is high when the smps output is in regulation. pgood2 is high when vtt is in regulation. 6 h l h smps is in forced-pwm mode. vtt is off and is in high impedance. pgood2 is forced low. vttr is active and regulates to v csl /2 or v refin . 7 h l l smps is in skip mode. vtt is off and is high impedance. pgood2 is forced low. vttr is active and regulates to v csl /2 or v refin . 8 h  l h x skip mode is exited as the max17000a ramps the output down to zero. vttr tracks v csl /2 or v refin during shutdown. after the smps output reaches 25mv, dl goes low. 9 h  l l x skip mode is exited as the max17000a ramps the output down to zero. vttr tracks v csl /2 or v refin during shutdown. after the smps output reaches 25mv, dl goes low. vtt is not enabled throughout soft-shutdown. 10 l x x dl low. internal16  discharge mosfets on csl and vtt enabled if ovp is high, but disable d if ovp is low. table 3. operating mode truth table downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 16 maxim integrated detailed description the max17000a complete ddr solution comprises astep-down controller, a source-sink ldo regulator, and a reference buffer. maxims proprietary quick-pwm pulse- width modulator in the max17000a is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the quick-pwm architecture circumvents the poor load-tran- sient timing problems of fixed-frequency current-mode pwms, while also avoiding the problems caused by widely varying switching frequencies in conventional con- stant-on-time and constant-off-time pwm schemes. figure 1 is the max17000a standard application circuit and figure 2 is the max17000a functional diagram. the max17000a includes a 2a source-sink ldo reg-ulator for the memory termination rail. the source-sink regulator features a dead band that either sources or sinks, ideal for the fast-changing short-period loads presenting in memory termination applications. this feature also reduces the vtt output capacitance requirement down to 1f, though load-transient response can still require higher capacitance values between 10f and 20f. the reference buffer sources and sinks 3ma, generating a reference rail for use in the memory controller and memory devices. dh v dd v cc ton on/off fb bst v in 7v to 20v vddq +1.8v or 1.5v pgnd1 dl lx csl c in n h n l r fba r fbb c vtti c vtt c vttr 0.33 f l1 r eq c eq r c d1 pgnd2 vtti vttr vtts +5v slp_s3# vtt +1v to + 2.5v vtt = vddq/2 stdby shdn skip refin pgood2 +5v pgood1 agnd fb options: 1. connect fb to 5v for fixed +1.8v. 2. connect fb to gnd for fixed +1.5v. 3. use fb resistor-divider for adjustable output voltages. r ton csh 5v v cc v cc ovp 1 12 1618 4 24 76 20 1415 1713 2322 21 19 10 9 23 ep 11 5 8 c bst 0.1 f r3 100k r2 100k r1 10 c vdd 1 f c vcc 1 f agnd pgnd c out max17000a vttr = vddq/2 r cs = r c r dcr r eq + r c r dcr = l1 x ( 1 + 1 ) c eq r eq r c figure 1. max17000a standard application circuit downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 17 maxim integrated vtt pos current limit vtt ss current limit vtt neg current limit bst lx v dd one-shot trig q t off(min) csl ton zero crossing ea shdn valley current limit pgnd1 sr q sr q dh 1mv20mv soft-start/ soft-stop dl csl csh 1v ref agnd v cc int_ref fb fb decode int_fb vtti vtt pgnd2 vttr power-good1 pgood1 1.15v ovf power-good2 pgood2 smps fault detection 1.2v ovp smps fault latch smps fault 0.7v int_fb ovf uvf vtts v dd v dd csl vtt window comparator vttr window comparator vtt fault smps fault 5ms timer vtt fault vttr vtt fault vtti vtt pgnd2 skip one-shot trig q ton error amp on-time compute smps run 10ms timer run 1.4ms 5mv vtt pgnd2 stdby pgnd1 pgnd2 vtt csl 16 16 refin csl r r 5mv vtt_en vtt_en run ovp v cc uvlo max17000a v dd - 0.3v figure 2. max17000a functional diagram downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 18 maxim integrated +5v bias supply (v dd , v cc ) the max17000a requires an external 5v bias supply inaddition to the battery. typically, this 5v bias supply is the notebooks 95% efficient 5v system supply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associated with the 5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the 5v supply can be generated with an external linear regulator such as the max1615. the 5v bias supply powers both the pwm controller and internal gate-drive power, so the maximum current drawn is: i bias = i q + f sw q g(mosfets) = 2ma to 20ma (typ) where i q is the current for the pwm control circuit, f sw is the switching frequency, and q g(mosfets) is the total gate-charge specification limits at v gs = 5v for the internal mosfets. free-running constant-on-time pwm controller with input feed-forward the quick-pwm control architecture is a pseudo-fixed-frequency, constant on-time, current-mode regulator with voltage feed-forward. this architecture utilizes the output filter capacitors esr to act as a current-sense resistor, so the output ripple voltage can provide the pwm ramp signal. in addition to the general quick- pwm, the max17000a also senses the inductor current through dcr method or with a sensing resistor. therefore, it is less dependent on the output capacitor esr for stability. the control algorithm is simple: the high-side switch on-time is determined solely by a one- shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. another one-shot sets a minimum off-time (250ns typ). the on-time one-shot is triggered if the error compara- tor is low, the low-side switch current is below the valley current-limit threshold, and the minimum off-time one- shot has timed out. on-time one-shot the heart of the pwm core is the one-shot that sets thehigh-side switch on-time. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltages. the high-side switch on-time is inversely proportional to the battery voltage as measured by the v in input, and proportional to the output voltage.an external resistor between the input power source and ton pin sets the switching frequency per phase according to the following equation: where c ton = 16.26pf, and 0.075v is an approxima- tion to accommodate for the expected drop across thelow-side mosfet switch. this algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. for loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switch- ing frequency is: where v dis is the sum of the parasitic voltage drops in the inductor discharge path, including synchronousrectifier, inductor, and pcb resistances; v chg is the sum of the parasitic voltage drops in the charging path,including the high-side switch, inductor, and pcb resis- tances; and t on is the on-time calculated by the max17000a. automatic pulse-skipping mode ( skip = agnd) in skip mode ( skip = agnd), an inherent automatic switchover to pfm takes place at light loads. thisswitchover is affected by a comparator that truncates the low-side switch on-time at the inductor currents zero crossing. dc output-accuracy specifications refer to the thresh- old of the error comparator. when the inductor is in continuous conduction, the max17000a regulates the valley of the output ripple, so the actual dc output volt- age is higher than the trip level by 50% of the output ripple voltage. in discontinuous conduction ( skip = agnd and i out < i load(skip) ), the output voltage has a dc regulation level higher than the error-comparatorthreshold by approximately 1.5% due to slope compen- sation. however, the internal integrator corrects for most of it, resulting in very little load regulation. the max17000a always uses skip mode during start- up, regardless of the skip and stdby setting. the skip and stdby controls take effect after soft-start is done. see figure 3. f vv tvv v sw out dis on in chg dis = + + () f cr k sw ton ton = + 1 65 (. ) t cr kv v v on ton ton csl in = + + (. ) (.) 65 0075 downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 19 maxim integrated forced-pwm mode ( skip = v cc ) the low-noise forced-pwm mode ( skip = v cc ) disables the zero-crossing comparator, which controls the low-side switch on-time. this forces the low-side gate-drive waveform to constantly be the complement of the high- side gate-drive waveform, so the inductor current reverses at light loads while dh maintains a duty factorof v out /v in . the benefit of forced-pwm mode is to keep a fairly constant switching frequency. however, forced-pwm operation comes at a cost: the no-load 5v bias current remains between 2ma to 20ma, depending on the switching frequency. stdby = agnd overrides the skip pin setting, forcing the max17000a into standby.the max17000a switches to forced-pwm mode during shutdown, regardless of the state of skip and stdby levels. standby mode ( stdby ) it should be noted that standby mode in themax17000a corresponds to computer system standby operation, and is not referring to the max17000a shut- down status. when standby mode is enabled ( stdby = agnd), vtt is disabled (high impedance) but vttr remainsactive. when standby mode is disabled ( stdby = v cc ), the vtt block is enabled and the vtt output capacitor ischarged. the vtt soft-start current limit increases lin- early from zero to its maximum current limit in 160s (typ), keeping the input vtti inrush low. see figure 4. inductor current i load = i peak /2 on-time 0 time i peak l v in - v out i t = figure 3. pulse-skipping/discontinuous crossover point stdby vttr output smps output pgood1 standby timing vtt outputvtt current limit pgood2 160 s vtt high-impedance figure 4. max17000a standby mode timing downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 20 maxim integrated valley current-limit protection the max17000a uses the same valley current-limit pro-tection employed on all maxim quick-pwm controllers. if the current exceeds the valley current-limit threshold, the pwm controller is not allowed to initiate a new cycle. the actual peak current is greater than the valley cur- rent-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit charac- teristic and maximum load capability are a function of the inductor value and battery voltage. when combined with the undervoltage-protection circuit, this current-limit method is effective in almost every circumstance. in forced-pwm mode, the max17000a also implements a negative current limit to prevent excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is set to approximately115% of the positive current limit. see figure 5. power-good outputs (pgood1 and pgood2) the max17000a features two power-good outputs.pgood1 is the open-drain output for a window com- parator that continuously monitors the smps output. pgood1 is actively held low in shutdown and during soft-start and soft-shutdown. after the soft-start termi- nates, pgood1 becomes high impedance as long as the smps output voltage is between 115% (typ) and 85% (typ) of the regulation voltage. when the smps output voltage exceeds the 115%/85% regulation win- dow, the max17000a pulls pgood1 low. any fault condition on the smps output forces pgood1 and pgood2 low and latches off until the fault latch is cleared by toggling shdn or cycling v cc power below 1v. detection of an ovp event immediately pullspgood1 low, regardless of the ovp state (ovp enabled or disabled). pgood2 is the open-drain output for a window com-parator that continuously monitors the vtt output. pgood2 is actively held low in standby, shutdown, and during soft-start. pgood2 becomes high imped- ance as long as the vtt output voltage is within 10% of the regulation voltage. when the vtt output exceeds the 10% threshold, the max17000a pulls pgood2 low. if pgood2 remains low for 5ms (typ), the max17000a latches off with the soft-shutdown sequence. for logic-level output voltages, connect an external 100k pullup resistor from pgood1 and pgood2 to v dd . por, uvlo power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and soft-startcircuit and preparing the controller for power-up. when ovp protection is enabled, a rising edge on por turns on the 16 discharge mosfet on csl and vtt. when ovp is disabled, the internal 16 discharge mosfets on csl and vtt also remain off.v cc undervoltage lockout (uvlo) circuitry inhibits switching until v cc reaches 4.1v (typ). when v cc rises above 4.1v, the controller activates the pwm controllerand initializes soft-start. when v cc drops below the uvlo threshold (falling edge), the controller stops, dlis pulled low, and the internal 16 discharge mosfets on the csl and vtt outputs are enabled, ifovp is enabled. soft-start and soft-shutdown soft-start and soft-shutdown for the max17000a pwmblock is voltage based. soft-start begins when shdn is driven high. during soft-start, the pwm output isramped up from 0v to the final set voltage in 1.4ms. this reduces inrush current and provides a predictable ramp-up time for power sequencing. the max17000a always uses skip mode during startup, regardless of the skip and stdby setting. the skip and stdby con- trols take effect after soft-start is done.the max17000a vtt ldo regulator uses a current-limit- ed soft-start function. when the vtt block is enabled, the internal source and sink current limits are linearly increased from zero to the full-scale limit in 160s. full- scale current limit is available when the vtt output is in regulation, or after 160s, whichever is earlier. the vttr reference buffer does not have any soft-start control. inductor current i limit i load 0 time i peak i lim(val) = i load(max) 1- lir 2 () figure 5. valley current-limit threshold point downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 21 maxim integrated soft-shutdown begins after shdn goes low, an output undervoltage fault occurs, or a thermal fault occurs. afault on the smps (uv fault for more than 200s (typ)), or fault on the vtt output that persists for more than 5ms (typ), triggers shutdown of the whole ic. during soft-shutdown, the output is ramped down to 0v in 2.8ms, reducing negative inductor currents that can cause negative voltages on the output. at the end of soft-shutdown, dl is driven low. when ovp is enabled (ovp = v cc ), the internal 16 discharging mosfets on csl and vtt are enableduntil startup is triggered again by a rising edge of shdn . when ovp is disabled (ovp = agnd), the csl and vtt internal 16 discharging mosfets are not enabled in shutdown. output fault protection the max17000a provides overvoltage/undervoltagefault protections for the pwm output. drive ovp to enable and disable fault protection as shown in table 4. stdby int_ref smps output refoksmps_runok pgood1 160 s shdn vtt outputvttr output dl vtt current limit pgood2 1.4ms 2.8ms vtt 16 fet skip fpwm csl 16 fet 25mv figure 6. max17000a startup/shutdown timing with ovp enabled downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 22 maxim integrated ovp mode reaction/driver state comment shutdown ( shdn = low) dl immediately pulled low. vttr tracks the smps output during soft-shutdown. csl and vtt are high impedance at the end of soft-shutdown (16  discharge mosfets disabled). outputs high- impedance in shutdown. smps uvp dl immediately pulled low. vttr tracks the smps output during soft-shutdown. csl and vtt are high impedance at the end of soft-shutdown (16  discharge mosfets disabled). smps latched fault condition. smps ovp (disabled) controller remains active (normal operation). note: an ovp detection still pulls pgood1 low. only pgood1 pulled low; fault not latched. vtt < -90% or vtt > +110% pgood2 immediately pulled low. soft-shutdown initiated if fault persists for more than 5ms (ty p). dh not used in soft-shutdown. dl low after soft-shutdown completed. vttr tracks the smps output soft-shutdown. vtt latched fault condition if fault persists for more than 5ms (typ). ovp disabled discharge disabled (ovp = low) v cc uvlo falling edge dl and dh immediately pulled low. pgood1 and pgood2 immediately forced low. vtt and vttr blocks immediately disabled (high impedance, no 16  discharge on outputs). shutdown ( shdn = low) soft-shutdown initiated. dl high after soft-shutdown completed. vttr tracks the smps output during soft-shutdown. internal 16  discharge mosfets on csl and vtt enabled after soft-shutdown. 16  discharge mosfets on csl and vtt enabled in shutdown. smps uvp soft-shutdown initiated. dh not used in soft-shutdown. dl low after soft-shutdown completed. vttr tracks the smps output during soft-shutdown. internal 16  discharge mosfets on csl and vtt enabled after soft-shutdown. smps latched fault condition. smps ovp (enabled) dl immediately latched high, dh forced low. pgood1 and pgood2 immediately forced low. vtt and vttr blocks immediately shut down. internal 16  discharge mosfets on csl and vtt enabled. smps latched fault condition. ovp enabled discharge enabled (ovp = high) vtt < 90% or vtt > 110% pgood2 immediately pulled low. soft-shutdown initiated if fault persists for more than 5ms (ty p). dh not used in soft-shutdown. dl low after soft-shutdown completed. vttr tracks the smps output during soft-shutdown. internal 16  discharge mosfets on csl and vtt enabled after soft-shutdown. vtt latched fault condition if fault persists for more than 5ms (typ). ovp enabled discharge enabled (ovp = high) v cc uvlo falling edge dl and dh immediately pulled low. pgood1 and pgood2 immediately forced low. vtt and vttr blocks immediately disabled. internal 16  discharge mosfets on csl and vtt enabled immediately. table 4. fault protection and shutdown setting truth table downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 23 maxim integrated smps overvoltage protection (ovp) if the output voltage of the smps rises 115% above itsnominal regulation voltage while ovp is enabled (ovp = v cc ), the controller sets its overvoltage fault latch, pulls pgood1 and pgood2 low, and forces dl high. thevtt and vttr block shut down immediately, and the internal 16 discharge mosfets on csl and vtt are turned on. if the condition that caused the overvoltagepersists (such as a shorted high-side mosfet), the bat- tery fuse blows. cycle v cc below 1v or toggle shdn to clear the overvoltage fault latch and restart the controller.ovp is disabled when ovp is connected to agnd (table 4). pgood1 upper threshold remains active at 115% of nominal regulation voltage even when ovp is disabled and the 16 discharge mosfets on csl and vtt are not enabled in shutdown. smps undervoltage protection (uvp) if the output voltage of the smps falls below 85% of itsregulation voltage for more than 200s (typ), the controller sets its undervoltage fault latch, pulls pgood1 and pgood2 low, and begins soft-shutdown pulsing dl. dh remains off during the soft-shutdown sequence initiated by an undervoltage fault. after soft-shutdown has com- pleted, the max17000a forces dl and dh low, and enables the internal 16 discharge mosfets on csl and vtt. cycle v cc below 1v or toggle shdn to clear the undervoltage fault latch and restart the controller. vtt overvoltage and undervoltage protection if the output voltage of the vtt regulator exceeds10% of its regulation voltage for more than 5ms (typ), the controller sets its fault latch, pulls pgood1 and pgood2 low, and begins soft-shutdown pulsing dl. dh remains off during the soft-shutdown sequence initi- ated by an undervoltage fault. after soft-shutdown has completed, the max17000a forces dl and dh low, andenables the internal 16 discharge mosfets on csl and vtt. cycle v cc below 1v or toggle shdn to clear the undervoltage fault latch and restart the controller. thermal-fault protection the max17000a features a thermal-fault protection cir-cuit. when the junction temperature rises above +160c, a thermal sensor activates the fault latch, pulls pgood1 and pgood2 low, and shuts down using the shutdown sequence. toggle shdn or cycle v cc power below v cc por to reactivate the controller after the junction temperature cools by 15c. design procedure firmly establish the input voltage range and maximumload current before choosing a switching frequency and inductor operating point (ripple-current ratio). the pri- mary design trade-off lies in choosing a good switching frequency and inductor operating point, and the follow- ing four factors dictate the rest of the design: input voltage range: the maximum value (v in(max) ) must accommodate the worst-case input supply voltage allowed by the notebooks acadapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage afterdrops due to connectors, fuses, and battery selec- tor switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses andfiltering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continu- ous load current (i load ) determines the thermal ovp mode reaction/driver state comment thermal fault dl and dh immediately pulled low. pgood1 and pgood2 immediately forced low. vtt and vttr blocks immediately disabled (high impedance, no 16  discharge on outputs). active-fault condition. v cc uvlo rising edge activate int_ref once v cc rises above uvlo, and shdn = high. once refok is valid (high), initiate the soft-start sequence. dl remains low until switching/soft-start begins. v cc por rising edge dl forced low. general shutdown and fault conditions v cc por falling edge dl = dont care. v cc less than 2vt is not sufficient to turn on the mosfets. table 4. fault protection and shutdown setting truth table (continued) downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 24 maxim integrated stresses and thus drives the selection of inputcapacitors, mosfets, and other critical heat-con- tributing components. most notebook loads gener- ally exhibit i load = i load(max) x 80%. switching frequency: this choice determines the basic trade-off between size and efficiency. theoptimal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in 2 . the opti- mum frequency is also a moving target, due torapid improvements in mosfet technology that are making higher frequencies more practical. inductor operating point: this choice provides trade-offs between size vs. efficiency and transientresponse vs. output noise. low inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduc- tion (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction bene- fit. the optimum operating point is usually found between 20% and 50% ripple current. inductor selection the switching frequency and operating point (% ripplecurrent or lir) determine the inductor value as follows: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. thecore must be large enough not to saturate at the peak inductor current (i peak ): setting the valley current limit the minimum current-limit threshold must be highenough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half the ripple current; therefore:where i limit(low) equals the minimum current-limit threshold voltage divided by the output sense element(inductor dcr or sense resistor). the valley current limit is fixed at 17mv (min) across the csh to csl differential input. special attention must be made to the tolerance and thermal variation of the on-resistance in the case of dcr sensing. use the worst-case maximum value for r dcr from the inductor data sheet, and add some margin forthe rise in r dcr with temperature. a good general rule is to allow 0.5% additional resistance for each degreecelsius of temperature rise, which must be included in the design margin unless the design includes an ntc thermistor in the dcr network to thermally compensate the current-limit threshold. the current-sense method (figure 7) and magnitude determine the achievable current-limit accuracy and power loss. the sense resistor can be determined by: r sense = v limit /i limit ii limit low load max () () > ? ? ? ? ? ? 1- lir 2 ii lir peak load max = + ? ? ? ? ? ? () 1 2 l vv fi l i r v v in out sw load max out in = ? ? ? ? ? ? ? - () ?? ? ? ? ? sense resistor l c out input (v in ) c in csl csh pgnd1 dl dh lx c eq r eq n h n l d l l esl r sense c eq r eq = l esl r sense a) output series resistor sensing max17000a figure 7a. current-sense configurations (sheet 1 of 2) downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 25 maxim integrated for the best current-sense accuracy and overcurrentprotection, use a 1% tolerance current-sense resistor between the inductor and output as shown in figure 7a. this configuration constantly monitors the inductor cur- rent, allowing accurate current-limit protection. however, the parasitic inductance of the current-sense resistor can cause current-limit inaccuracies, especially when using low-value inductors and current-sense resistors. this parasitic inductance (l esl ) can be can- celled by adding an rc circuit across the sense resis-tor with an equivalent time constant: alternatively, low-cost applications that do not require highly accurate current-limit protection could reduce the overall power dissipation by connecting a series rc circuit across the inductor (figure 7b) with an equiva- lent time constant: and: where r cs is the required current-sense resistance, and r dcr is the inductors series dc resistance. use the worst-case inductance and r dcr values provided by the inductor manufacturer, adding some margin forthe inductance drop over temperature and load. mosfet gate drivers (dh, dl) the dh and dl drivers are optimized for driving moder-ate-sized high-side, and larger low-side power mosfets. this is consistent with the low duty factor seen in note- book applications, where a large v in - v out differential exists. the high-side gate driver (dh) sources and sinks1.2a, and the low-side gate driver (dl) sources 1.0a and sinks 2.4a. this ensures robust gate drive for high-cur- rent applications. the dh floating high-side mosfet dri- ver is powered by an internal boost switch charge pump at bst, while the dl synchronous-rectifier driver is pow- ered directly by the 5v bias supply (v dd ). pwm output capacitor selection the output filter capacitor must have low enough effec-tive series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. in core and chipset converters and other applications where the output is subject to large-load transients, the output capacitors size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in low-power applications, the output capacitors size often depends on how much esr is needed to maintain an acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capaci- tors esr. rr v i esr pcb step load max + () () r l crr dcr eq =+ ? ? ? ? ? ? 1 1 1 2 r r rr r cs dcr = + 2 12 cr l r eq eq esl sense = c out input (v in ) c in b) lossless inductor sensing for thermal compensation: r2 should consist of an ntc resistor in series with a standard thin-film resistor. csl csh pgnd1 dl dh lx c eq r 1 r 2 n h n l d l l inductor r dcr r cs = r2 r dcr r1 + r2 r dcr = l [ 1 + 1 ] c eq r1 r2 max17000a figure 7b. current-sense configurations (sheet 2 of 2) downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 26 maxim integrated the maximum esr to meet ripple requirements is:where f sw is the switching frequency. with most chemistries (polymer, tantalum, aluminum,electrolytic), the actual capacitance value required relates to the physical size needed to achieve low esr and the chemistry limits of the selected capacitor tech- nology. ceramic capacitors provide low esr, but the capacitance and voltage rating (after derating) are determined by the capacity needed to prevent v sag and v soar from causing problems during load tran- sients. generally, once enough capacitance is addedto meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. thus, the out- put capacitor selection requires carefully balancing capacitor chemistry limitations (capacitance vs. esr vs. voltage rating) and cost. pwm output capacitor stability considerations for quick-pwm controllers, stability is determined by thein-phase feedback ripple relative to the switching frequen- cy, which is typically dominated by the output esr. the boundary of instability is given by the following equation: where c out is the total output capacitance, r esr is the total equivalent series resistance of the output capaci-tors, r sense is the effective current-sense resistance (see figure 7), and a cs is the current-sense gain of 2. for a standard 300khz application, the effective zerofrequency must be well below 95khz, preferably below 50khz. with these frequency requirements, standard tantalum and polymer capacitors already commonly used have typical esr zero frequencies below 50khz, allowing the stability requirements to be achieved with- out any additional current-sense compensation. in the standard application circuit (figure 1), the esr needed to support a 15mv p-p ripple is 15mv/(10a x 0.3) = 5m . two 330f, 9m polymer capacitors in parallel provide 4.5m (max) esr and 1/(2 x 330f x 9m ) = 53khz esr zero frequency.ceramic capacitors have a high-esr zero frequency, but applications with sufficient current-sense compen- sation can still take advantage of the small size, low esr, and high reliability of the ceramic chemistry. by the inductor current dcr sensing, applications with ceramic output capacitors can be compensated usingeither a dc-compensation or ac-compensation method. the dc-coupling requires fewer external com- pensation capacitors, but this also creates an output load line that depends on the inductors dcr (parasitic resistance). alternatively, the current-sense information can be ac-coupled, allowing stability to be dependent only on the inductance value and compensation com- ponents and eliminating the dc load line. when only using ceramic output capacitors, output overshoot (v soar ) typically determines the minimum output capacitance requirement. their relatively lowcapacitance value can allow significant output over- shoot when stepping from full-load to no-load condi- tions, unless a small inductor value and high switching frequency are used to minimize the energy transferred from inductor to capacitor during load-step recovery. unstable operation manifests itself in two related, but distinctly different ways: double pulsing and feedback loop instability. double pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this fools the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response undervoltage/overshoot. input capacitor selection the input capacitor must meet the ripple currentrequirement (i rms ) imposed by the switching currents. the i rms requirements can be determined by the fol- lowing equation:the worst-case rms current requirement occurs when operating with v in = 2v out . at this point, the above equation simplifies to: i rms = 0.5 x i load i i v vvv rms load in out in out = ? ? ? ? ? ? () rrar eff esr cs sense =+ f rc sw eff out 1 2 r vf l vv v v esr in sw in out out ripp () ? ? ? ? ? ? ? ? - l le downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 27 maxim integrated for most applications, nontantalum chemistries (ceramic,aluminum, or os-con) are preferred due to their resis- tance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. if the quick-pwm controller is operated as the second stage of a two-stage power-conversion system, tanta- lum input capacitors are acceptable. in either configu- ration, choose an input capacitor that exhibits less than +10c temperature rise at the rms input current for optimal circuit longevity. mosfet selection most of the following mosfet guidelines focus on thechallenge of obtaining high load-current capability when using high-voltage (> 20v) ac adapters. low- current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at bothv in(min) and v in(max) . calculate both these sums. ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of n h (reducing r ds(on) but with higher c gate ). conversely, if the loss- es at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of n h (increasing r ds(on) to lower c gate ). if v in does not vary over a wide range, the minimum power dissipation occurswhere the resistive losses equal the switching losses. choose a low-side mosfet that has the lowest possi- ble on-resistance (r ds(on) ), comes in a moderate-sized package (i.e., one or two 8-pin sos, dpak, or d 2 pak), and is reasonably priced. make sure that the dl gatedriver can supply sufficient current to support the gate charge and the current injected into the parasitic gate- to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems can occur (see the mosfet gate drivers (dh, dl) section). mosfet power dissipation worst-case conduction losses occur at the duty factorextremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at theminimum input voltage: generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power dissipation often limits how small the mosfet can be. again, the optimum occurs when the switchinglosses equal the conduction (r ds(on) ) losses. high- side switching losses do not usually become an issueuntil the input is greater than approximately 15v. calculating the power dissipation in high-side mosfet (n h ) due to switching losses is difficult since it must allow for difficult quantifying factors that influence theturn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pcb layout characteristics. the following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on n h : where c oss is the n h mosfets output capacitance, q g(sw) is the charge needed to turn on the n h mosfet, and i gate is the peak gate-drive source/sink current (2.2a typ).switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the c x v in 2 x f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when biased fromv in(max) , consider choosing another mosfet with lower parasitic capacitance.for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage:the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) , but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro-tect against this possibility, the circuit can be over designed to tolerate: ii i load valley max inductor =+ ? ? ? ? ? ? () 2 () () =+ ? ? ? ? ? ? i il i r valley max load max 2 pd (nl resistive) = 1 ? ? ? ? ? ? ? ? ? ? v v out in max () ?? ? ? ? () ir load ds on 2 () pd (nh switching) = v i f q in max load sw gsw () ( )) i c gate o ? ? ? ? ? ? + s ss in sw vf 2 2 pd (nh resistive) = v v i out in load ? ? ? ? ? ? () 2 rr ds on () downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 28 maxim integrated where i valley(max) is the maximum valley current allowed by the current-limit circuit, including thresholdtolerance and on-resistance variation. the mosfets must have a good size heatsink to handle the overload power dissipation. choose a schottky diode (dl) with a forward voltage low enough to prevent the low-side mosfet body diode from turning on during the dead time. select a diode that can handle the load current during the dead times. this diode is optional and can be removed if effi- ciency is not critical. setting the pwm output voltage preset output voltages the max17000as dual mode? operation allows theselection of common voltages without requiring external components. connect fb to agnd for a fixed 1.5v out- put, to v cc for a fixed 1.8v output, or connect fb directly to out for a fixed 1.0v output. adjustable output voltage the output voltage can be adjusted from 1.0v to 2.7vusing a resistive voltage-divider (figure 8). the max17000a regulates fb to a fixed reference voltage (1.0v). the adjusted output voltage is: where v fb is 1.0v. vtti input capacitor stability considerations the value of the vtti bypass capacitor is chosen tolimit the amount of ripple/noise at vtti, and the amount of voltage dip during a load transient. typically, vtti is connected to the output of the buck regulator, which already has a large bulk capacitor. nevertheless, a ceramic capacitor of equivalent value to the vtt output capacitor must be used and must be added and placed as close as possible to the vtti pin. this value must be increased with larger load current, or if the trace from the vtti pin to the power source is long and has significant impedance. setting vtt output voltage the vtt output stage is powered from the vtti input.the output voltage is set by the refin input. refin sets the feedback regulation voltage (vttr = vtts = v refin ) of the max17000a. connect a 0.1v to 2.0v volt- age input to set the adjustable output for vtt, vtts, andvttr. if refin is tied to v cc , the internal csl/2 divider is used to set vtt voltage; hence, vtt tracks the v csl voltage and is set to v csl /2. this feature makes the max17000a ideal for memory applications in which thetermination supply must track the supply voltage. vtt output capacitor selection a minimum value of 9f is needed to stabilize a 300mavtt output. this value of capacitance limits the regula- tors unity-gain bandwidth frequency to approximately 1.2mhz (typ) to allow adequate phase margin for stabil- ity. to keep the capacitor acting as a capacitor within the regulators bandwidth, it is important that ceramic capacitors with low esr and esl be used. vv r r out fb fba fbb =+ ? ? ? ? ? ? 1 fb v out pgnd1 dl lx csl c out l1 n l d1 r fba r fbb csh max17000a figure 8. setting v out with a resistive voltage-divider dual mode is a trademark of maxim integrated products, inc. downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 29 maxim integrated since the gain bandwidth is also determined by thetransconductance of the output fets, which increases with load current, the output capacitor might need to be greater than 20f if the load current exceeds 1.5a, but can be smaller than 20f if the maximum load current is less than 1.5a. as a guideline, choose the minimum capacitance and maximum esr for the output capaci- tor using the following: c out_min needs to be increased by a factor of 2 for low-dropout operation:r esr_max value is measured at the unity-gain-band- width frequency given by approximately:once these conditions for stability are met, additional capacitors, including those of electrolytic and tantalum types, can be connected in parallel to the ceramic capacitor (if desired) to further suppress noise or volt- age ripple at the output. vttr output capacitor selection the vttr buffer is a scaled-down version of the vttregulator, with much smaller output transconductance. its compensation capacitor can, therefore, be smaller and its esr larger than what is required for its larger counterpart. for typical applications requiring load cur- rent up to 4ma, a ceramic capacitor with a minimum value of 0.33f is recommended (r esr < 0.3 ). connect this capacitor between vttr and the analogground plane. power dissipation power loss in the max17000a is the sum of the lossesof the pwm block, the vtt ldo block, and the vttr reference buffer: the 2w total power dissipation is within the 24-pintqfn multilayer board power dissipation specification of 2.22w. the typical application does not source or sink continuous high currents. vtt current is typically 100ma to 200ma in the steady state. vttr is down in the microamp range, though the intel specification requires 3ma for ddr1 and 1ma for ddr2. true worst- case power dissipation occurs on an output short-circuit condition with worst-case current limit. the max17000a does not employ any foldback current limiting, and relies on the internal thermal shutdown for protection. both the vtt and vttr output stages are powered from the same vtti input. their output voltages are refer- enced to the same refin input. the value of the vtti bypass capacitor is chosen to limit the amount of rip- ple/noise at vtti, or the amount of voltage dip during a load transient. typically, vtti is connected to the output of the buck regulator, which already has a large bulk capacitor. boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate-charging requirements ofthe high-side mosfets. typically, 0.1f ceramic capacitors work well for low-power applications driving medium-sized mosfets. however, high-current appli- cations driving large, high-side mosfets require boost capacitors larger than 0.1f. for these applications, select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high- side mosfets gates: where q gate is the total gate charge specified in the high-side mosfets data sheet. for example, assumethe fds6612a n-channel mosfet is used on the high side. according to the manufacturers data sheet, a sin- gle fds6612a has a maximum gate charge of 13nc (v gs = 5v). using the above equation, the required boost capacitance would be:selecting the closest standard value, this example requires a 0.1f ceramic capacitor. c nc mv f bst == 13 200 0 065 . c q mv bst gate = 200 pd total w () = 2 pd vttr ma v mw () . . == 30 92 7 pd vtt a v w () . . = = 20918 pd pwm i v ma v w bias () . == = 54 0 502 f c i a gbw out load = 36 15 . rm a i esr max load _ . = 5 15 cf i a out min load _ . = 20 15 downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 30 maxim integrated applications information pcb layout guidelines careful pcb layout is critical to achieve low switchinglosses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all the power components on the topside of the board, with their ground terminals flush against one another. follow these guidelines for good pcb layout: ? keep the high-current paths short, especially at the ground terminals. this practice is essential for sta-ble, jitter-free operation. ? keep the power traces and load connections short. this practice is essential for high efficiency. usingthick copper pcbs (2oz vs. 1oz) can enhance full- load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. ? minimize current-sensing errors by connecting csh and csl directly across the current-sense resistor(r sense ). ? when trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to bemade longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. ? route high-speed switching nodes (bst, lx, dh, and dl) away from sensitive analog areas (refin,fb, csh, and csl). layout procedure 1) place the power components first, with ground ter- minals adjacent (low-side mosfet source, c in , c out , and anode of the low-side schottky). if possi- ble, make all these connections on the top layerwith wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet, preferably on the backside opposite themosfets to keep lx, gnd, dh, and the dl gate- drive lines short and wide. the dl and dh gate traces must be short and wide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic) to keep the driver impedance low and for proper adaptive dead-time sensing. 3) group the gate-drive components (bst diode and capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figures 1 and 9. this diagram can beviewed as having two separate ground planes: power ground, where all the high-power compo- nents go; and an analog ground plane for sensitive analog components. the analog ground plane and power ground plane must meet only at a single point directly at the ic. 5) connect the output power planes directly to the out- put filter capacitor positive and negative terminalswith multiple vias. place the entire dc-to-dc con- verter circuit as close as is practical to the load. table 5 lists the design differences between themax17000 and max17000a. max17000 max17000a stdb = low turns off vtt and overrides the skip setting, forcing the smps to enter a low-quiescent current ultra-skip mode. stdb = low only turns off vtt rail, and does not affect smps operation. table 5. max17000 vs. max17000a design differences downloaded from: http:///
max17000a complete ddr2 and ddr3 memory power-management solution 31 maxim integrated kelvin sense vias under the inductor (see evaluation kit) via to power ground connect agnd and pgnd1 to the controller at the exposed pad connect the exposed pad to analog ground x-ray view. ic mounted on bottom side of pcb. power stage layout (top side of pcb) ic layout v dd bypass capacitor v cc bypass capacitor vtti bypass capacitor vtt bypass capacitor inductor l1 output smps c out input power ground c eq csl csh r2r1 r ntc kelvin-sense vias to inductor pad inductor dcr sensing c out c in1 figure 9. pcb layout example chip information transistor count: 7856process: bicmos package type package code outline no. land pattern no. 24 tqfn t2444-4 21-0139 90-0022 package information for the latest package outline information and land patterns (foot-prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only.package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 32 ________________________________ maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ? 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max17000a complete ddr2 and ddr3 memory power-management solution revision history revision number revision date description pages changed 0 10/08 initial release 1 12/08 modified stdby pin function 5, 11, 12, 13, 17, 23, 2 11/10 changed r esr_max equation 29 3 4/13 updated absolute maimum ratings 2 downloaded from: http:///


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